1. Field of the Invention
The present invention generally relates to data processing systems and more particularly to a system for priority determination among several contenders requesting use of a common bus.
2. Discussion of the Prior Art
In a system having a plurality of devices coupled over one or more common input/output buses, an orderly system must be provided by which bidirectional transfer of information may be provided between such devices. This problem becomes more and more complex when such devices include for example, a central processor unit, one or more main memory units and various types of peripheral devices, such as magnetic tape storage devices, disk storage devices, card reading equipment and the like.
All of these peripheral units must have access to the central processor or main memory at one time or another. Such access is usually accomplished by means of a common bus which may include a number of groups of wire lines, one group being used for addressed information, one group for data information and others for control function information. In order that utter chaos does not prevail, means must be provided for controlling the access to the common bus in accordance with a predetermine arrangement. Numerous schemes have been provided for effecting such control, exemplary of which is U.S. Pat. No. 3,886,524 to Daren R. Appelt, entitled "Asynchronous Communication Bus". Among the schemes provided for such control are polling schemes wherein the CPU polls the individual peripheral devices, in a predetermined sequence, to ascertain if any peripheral device has a need to access the common bus. The CPU then grants access to the common bus to one of the peripheral devices in accordance with a predetermined priority schedule.
In another type of scheme, a control signal is generated which is transmitted serially to the peripheral devices, wherein the order of priority is determined by the serial order along the serial string. One such scheme is shown in U.S. Pat. No. 3,832,692 to Russell A. Henzel, et al., entitled "Priority Network for Devices Coupled by a Multi-Line Bus". In the implementation of such computer systems, there is usually a separate I/O controller between each of the peripheal devices and the common bus. These I/O controllers are usually on a circuit card inserted in predetermined slots in a card cage. In a first type of access system, the address of a particular peripheral device is correlated with a predetermine one of the slots in the card cage. In other words, the central processor addresses a particular slot on the card cage to access a selected peripheral device. In the second type of scheme referenced above, while the selected address may well be on the individual card, the serial relationship imposes a restriction on the card slot arrangement. Since there is a requirement for the serial connection, the cards must be put into the slots in their priority order, beginning at the first slot with no gaps in the slots between the first and the last card. In both of these schemes, considerable time is required for the procedure of actually accessing the select peripheral devices to the common bus.
In a typical example, representative of computer systems currently in use, the common bus between master and slave units comprise a data channel of 16 parallel data lines and an address channel of 20 parallel address lines together with additional control lines. Typically, data lines, address lines and control lines total about 80 in number. Such systems involve the use of a central set of digital logic to perform all the tracing among requests entered into this system by various master units for access to the common bus for transfer of address or data information. U.S. Pat. No. 3,710,324, to John B. Cohen, et al., entitled "Data Processing System" discloses such a system.
Other systems exist in which arbitration logic networks are distributed throughout the system. Like logic sets are provided at each master unit in order to perform arbitration requests from several master units in the system. U.S. Pat. No. 3,886,524, to Appelt, discloses one such system and U.S. Pat. No. 4,030,075 to George J. Barlow, entitled "Data Processing System Having Distributed Priority Network", U.S. Pat. No. 3,997,896 to Frank V. Cassarino, Jr., et al., entitled "Data Processing System Providing Split Bus Cycle Operation" and U.S. Pat. No. 3,993,981, to Frank V. Cassarino, Jr., et al., entitled "Apparatus for Processing Data Transfer Requests in a Data Processing System", disclose another such system. Both of these systems have one or more lines connected in series in the order of assigned priority between the master units. Means are then provided to actuate the logic circuits via the control lines to limit access to the bus in the order of assigned priority and to communicate to other master units requesting access as to the availability of the common bus.
Various methods and apparatus are known in the prior art for interconnecting such a system. Such prior art systems range from those having common data bus paths to those having special paths between various devices. Such systems also include a capability of either synchronous or asynchronous operation in combination with the bus type. In addition, such systems normally include various parity checking apparatus, priority schemes and interrupt structures. One such structural scheme is shown in U.S. Pat. No. 3,866,181, to Byron G. Gayman, et al., entitled "Interrupt Sequencing Control Apparatus". A bus assignor for a data processing system utilizing a common bus is shown in U.S. Pat. No. 3,959,775 to John G. Valassis, et al., entitled "Multiprocessing System Implemented With Microprocessors". A system dealing with the scanning of interrupt signals is shown in U.S. Pat. No. 4,020,471 to William E. Woods, et al., entitled "Interrupt Scan And Processing System For A Data Processing System". Other priority schemes are shown in U.S. Pat. No. 3,996,561 to Krzysztof Kowal, et al., entitled "Priority Determination Apparatus for Serially Coupled Peripheral Interfaces in a Data Processing System", U.S. Pat. No. 4,028,663, to Robert D. Royer, et al., entitled "Digital Computer Arrangement for High Speed Memory Access", U.S. Pat. No. 3,931,613 to Ronald H. Gruner, et al., entitled "Data Processing System" and U.S. Pat. No. 3,447,135 to Salvatore A. Calta, et al., entitled "Peripheral Data Exchange".
The manner in which addressing is provided in such systems as well as the manner in which, for example, any one of the devices may control the data transfer is dependent upon the implementation of the system, i.e., whether there is a common bus, whether the operation thereof is synchronous or asynchronous, etc. The system's response and throughput capability is greatly dependent on these various structures.